1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to a technique for incorporating selective condition codes write back control features into an existing microprocessor instruction set architecture.
2. Description of the Related Art
Since microprocessors were fielded in the early 1970's, their use has grown exponentially. Originally employed in the scientific and technical fields, microprocessor use has gravitated from those specialty fields into commercial consumer fields that include products such as desktop and laptop computers, video game controllers, and a host of other common household and business devices.
Along with this explosive growth in use over the past 30 years, the art has experienced a corresponding technology pull that is characterized by an escalating demand for increased speed, expanded addressing capabilities, faster memory accesses, larger operand size, more operations (e.g., floating point, single-instruction multiple data (SIMD), conditional moves, etc.), and added specialty operations (e.g., multi-media operations). This technology pull has resulted in an incredible number of advances in the art which have been incorporated in microprocessor designs such as extensive pipelining, super-scalar architectures, cache structures, out-of-order processing, burst access, branch predication, and speculative execution. Quite frankly, a present day microprocessor is an amazingly complex and capable machine in comparison to its 30-year-old predecessors.
But unlike many other products, there is another very important factor that has constrained, and continues to constrain, the evolution of microprocessor architecture. This factor, legacy compatibility, moreover accounts for a great deal of complexity in a present day microprocessor. For market-driven reasons, many producers have opted to incorporate new architectural features into updated microprocessor designs, but at the same time in these newer products they choose to retain all of the capabilities that are required to insure compatibility with older, so-called legacy application programs.
Nowhere has this legacy compatibility burden been more noticeable than can be seen in the development history of x86-compatible microprocessors. It is well known that a present day virtual-mode, 32-/16-bit x86 microprocessor is still capable of executing 8-bit, real-mode, application programs which were produced during the 1980's. And those skilled in the art will also acknowledge that a significant amount of corresponding architectural “baggage” is carried along in the x86 architecture for the sole purpose of supporting compatibility with legacy applications and operating modes. Yet, while in the past developers have been able to incorporate newly developed architectural features into existing instruction set architectures, the means whereby use of these features is enabled-programmable instructions-are becoming scarce. More succinctly, there are no more “spare” instructions in certain instruction sets of interest that provide designers with a means to incorporate newer features into an existing architecture.
In the x86 instruction set architecture, for example, there are no undefined 1-byte opcode states that have not already been used. All 256 opcode states in the primary 1-byte x86 opcode map are taken up with existing instructions. As a result, x86 microprocessor designers must presently make a choice between providing new features and abandoning legacy compatibility. If new programmable features are to be provided, then they must be assigned to opcode states. And if spare opcode states do not remain in an existing instruction set architecture, then some of the existing opcode states must be redefined to provide for the new features. Thus, legacy compatibility is sacrificed in order to provide for new feature growth.
One area of growth that is yet to be addressed in many instruction set architectures is known as selective control of condition codes write back. In many present day instruction sets, there are a number of instructions that direct execution logic in a conforming microprocessor to perform operations on provided operands such as adding two operands together, or performing a logical AND operation on two operands. Regardless of the type of operation that is performed, the outcome is provided in terms of a result. And is often the case, application programs may take different paths of program flow depending upon certain attributes of a recently generated result. For example, flow may proceed to point A in a program if the result is a positive number and flow will proceed to point B if the result is a negative number. If the result is zero, then flow would proceed to point C.
Because the flow of application programs frequently is determined based upon whether a result reflects certain boundary conditions (e.g., negative, positive, zero, overflow, odd number of ones, even number of ones, and etc.), designers have historically provided means whereby boundary attributes of a recently computed result can be easily evaluated and program flow altered accordingly. The most prevalent means in use today for storing and checking result conditions is a series of condition code bits that are stored in a special register along with a number of conditional branch instructions that allow program flow to be altered according to the states of one or more of the bits in the special register. When an operation is executed and a corresponding result is generated, condition code logic in a microprocessor evaluates the corresponding result in view of each of the boundary conditions and sets corresponding bits in the special condition codes register for subsequent query by conditional branch instructions.
In many of today's microprocessors, the evaluation of results and update of condition codes registers are automatic. Each time a new result is computed, the state of the condition codes register (also known as a flags register) is updated to reflect the boundary attributes of the new result. And although this feature is quite useful in many cases, there are situations where update of a condition codes register following generation of a result is not desirable. For example, it is well known by those skilled in the art that evaluation of all of the boundary conditions and update of corresponding bits that are associated with each newly generated result is quite a complex and time consuming task, so much so that most microprocessors must stall their execution pipeline for one or more cycles each time a result is computed in order to complete the boundary conditions evaluation and to set condition codes bits accordingly. This fact is appreciated by both microprocessor designers and compiler designers. Hence, in situations where a conditional branch instruction (a condition code consumer) is immediately preceded by an instruction that establishes conditions for a branch (a condition code producer), most compilers and some microprocessors will look forward in the instruction flow to find one or more following instructions that do not affect condition codes and will insert these following instructions in between the condition code producing instruction and the conditional branch instruction so that code execution is scheduled more efficiently.
But one skilled in the art will appreciate that subsequent instructions cannot always be inserted and consequently, stalls in the pipeline do indeed occur frequently. This problem is only exacerbated when such situations occur within iterative program loops. And in situations where conditions have already been established for a branch, the insertion of unnecessary no-op instructions in a program flow proves to be disadvantageous in terms of the overall execution speed of an application program.
Therefore, what is needed is a technique that allows selective control of condition codes update to be incorporated into an existing microprocessor instruction set architecture, where the microprocessor instruction set is completely populated with defined opcodes, and where incorporation of the technique allows a conforming microprocessor to retain the capability to execute legacy application programs.
In another scenario, a programmer may desire to set up a condition upon which subsequent operations are to be based. Accordingly, it is desirable to maintain a set of condition codes throughout the execution of a series of instructions, where results generated by the series of instructions are not allowed to modify the condition codes that were previously established.